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rev. 4190a?8051?11/02 features 80c51 compatible ? three i/o ports ? two 16-bit timer/counters ? 256 bytes ram 4k bytes rom/otp program memory with 64 bytes encryption array and 3 security levels high-speed architecture ? 33 mhz at 5v (66 mhz equivalent) ? 20 mhz at 3v (40 mhz equivalent) ? x2 speed improvement capability (6 clocks/machine cycle) 10-bit, 8 channels a/d converter hardware watchdog timer programmable i/o mode: standard c51, input only, push-pull, open drain asynchronous port reset full duplex enhanced uart with baud rate generator spi, master mode dual system clock ? crystal or ceramic oscillator (33/40 mhz) ? internal rc oscillator (12 mhz) ? programmable prescaler programmable counter array with high-speed output, compare/capture, pulse width modulation and watchdog timer capabilities interrupt structure ? 8 interrupt sources ? 4 interrupt priority levels power control modes ? idle mode ? power-down mode ? power-off flag power supply: 2.7 - 5.5v temperature range: industrial (-40 to 85 o c) package: so24, dil24, ssop24 description the at8xc5111 is a high-performance rom/otp version of the 80c51 8-bit micro- controller in low pin count package. the at8xc5111 retains all the features of the standard 80c51 with 4k bytes rom/otp program memory, 256 bytes of internal ram, an 8-source, 4-level interrupt system, an on-chip oscillator and two timer/counters. the at8xc5111 is dedicated for analog interfacing applications. for this, it has a 10- bit, 8 channels a/d converter and a five-channel programmable counter array. in addition, the at8xc5111 has a hardware watchdog timer, a versatile serial chan- nel that facilitates multiprocessor communication (euart) with an independent baud rate generator, an spi serial bus controller and a x2 speed improvement mechanism. the x2 feature permits keeping the same cpu power at an oscillator frequency divided by two. the prescaler allows to decrease cpu and peripherals clock frequency. the fully static design of the at8xc5111 can reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the at8xc5111 has 3 software-selectable modes of reduced activity for further reduc- tion in power consumption. in the idle mode, the cpu is frozen while the peripherals are still operating. in the quiet mode, only the a/d converter is operating. low pin count 8-bit microcontroller with a/d converter at83c5111 at87c5111
2 at8xc5111 4190a ? 8051 ? 11/02 in the power-down mode, the ram is saved and all other functions are inoperative. two oscillator sources, crystal and rc, provide a versatile power management. the at8xc5111 is proposed in low-pin count packages. port 0 and port 2 (address/data buses) are not available . block diagram notes: 1. alternate function of port 1. 2. alternate function of port 3. 3. alternate function of port 4. timer 0 int ram 256 t0 t1 rxd txd xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core (2) (3) (2) (3) port 1 port 3 p1 p4 ib-bus watch dog vss vcc (2) (2) rom /otp 4k *8 x8 eci cex0-4 xtal osc rc osc (1) (1) port 4 p3 (2) (2) (2) pca miso (3) mosi (3) spsck (3) spi brg ss (3) rst/v pp a/d converter v ref ain0-7 (3) parallel i/o ports
3 at8xc5111 4190a ? 8051 ? 11/02 sfr mapping the special function registers (sfrs) of the at8xc5111 belong to the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p1, p3, p4, p1m1, p1m2, p3m1, p3m2, p4m1, p4m2 timer registers: tcon, th0, th1, tmod, tl0, tl1 serial i/o port registers: saddr, saden, sbuf, scon, brl, bdrcon power and clock control registers: ckcon0, ckcon1, osccon, cksel, pcon, ckrl interrupt system registers: ie, ie1, ipl0, ipl1, iph0, iph1 watchdog timer: wdtrst, wdtprg spi: spcon, spsta, spdat pca: ccap0l, ccap1l, ccap2l, ccap3l, ccap4l, ccap0h, ccap1h, ccap2h, ccap3h, ccap4h, ccapm0, ccapm1, ccapm2, ccapm3, ccapm4, cl, ch, cmod, ccon adc: adccon, adcclk, adcdath, adcdatl, adcf
4 at8xc5111 4190a ? 8051 ? 11/02 reserved table 1. sfr addresses and reset values 0/8 1/9 72/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccap2h xxxx xxxx ccap3h xxxx xxxx ccap4h xxxx xxxx ffh f0h b 0000 0000 adclk 0000 0000 adcon 0000 0000 addl xxxxxx00 addh 0000 0000 adcf 0000 0000 f7h e8h cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccap2l xxxx xxxx ccap3l xxxx xxxx ccap4l xxxx xxxx conf efh e0h acc 0000 0000 p1m2 0000 0000 p3m2 0000 0000 p4m2 0000 0000 e7h d8h ccon 00x0 0000 cmod x000 0000 ccapm0 00xx x000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 p1m1 0000 0000 p3m1 0000 0000 p4m1 0000 0000 d7h c8h cfh c0h p4 1111 1111 spcon 0001 0100 spsta xxxxxxxx spdat xxxx xxxx c7h b8h ipl0 0000 0000 saden 0000 0000 bfh b0h p3 1111 1111 ie1 0000 0000 ipl1 0000 0000 iph1 0000 0000 iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 ckcon1 xxxx xxx0 afh a0h auxr1 xxxxxxx0 wdrst 0000 0000 wdtprg 0000 0000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon 0000 0000 9fh 90h p1 1111 1111 ckrl 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon0 x000x000 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 cksel xxxx xxx1 osccon xxxx xx01 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
5 at8xc5111 4190a ? 8051 ? 11/02 pin configuration pin descriptions xtal1 p1.7/cex4 p4.7/ain7 1 vcc p1.6/cex3 p3.1/txd p1.3/cex0 p1.2/eci p1.4/cex1 p4.4/miso/ain4 p4.6/spsck/ain6 p4.5/mosi/ain5 p4.3/ int1 /ain3 p4.2/ ss /ain2 p4.1/ain1/t1 p4.0/ain0 p3.0/rxd 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p1.5/cex2 p3.3/t0 p3.2/int0 so24 dil24 vref vss rst /vpp xtal2 xtal2 xtal1 vref 1 avcc p1.6/cex3 p3.1/txd p1.3/cex0 p1.2/eci p1.4/cex1 p4.4/miso/ain4 p4.6/spsck/ain6 p4.5/mosi/ain5 p4.3/ int1 /ain3 p4.2/ ss /ain2 p4.1/ain1/t1 p4.0/ain0 p3.0/rxd 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p1.5/cex2 p3.3/t0 p3.2/int0 ssop24 vss avss vcc rst /vpp mnemonic type name and function v ss i ground: 0v reference v cc i power supply: this is the power supply voltage for normal, idle and power-down operation. vref i vref: a/d converter positive reference input rst /vpp i rst /v pp : reset/programming supply voltage: a low on this pin for two machine cycles while the oscillator is running, resets the device. this pin has no pull-up. in order to use the internal power-on reset, an external pull-up resistor must be connected. this pin also receives the 12v programming pulse which will start the eprom programming and the manufacturer test modes. xtal1 i xtal1 : input to the inverting oscillator amplifier and input to the internal clock generator circuits xtal2 o xtal2 : output from the inverting oscillator amplifier p1.2 - p1.7 i/o port 1: port 1 is an 6-bit programmable i/o port . see section ? ports ? , page 18 for a description of i/o ports. alternate functions for port 1 include: i/o eci (p1.2): external clock for the pca i/o cex0 (p1.3): capture/compare external i/o for pca module 0 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 i/o cex3 (p1.6): capture/compare external i/o for pca module 3 i/o cex4 (p1.7): capture/compare external i/o for pca module 4 p3.0 - p3.3 i/o port 3: port 3 is an 6-bit programmable i/o port with internal pull-ups. see section "ports", page 18 for a description of i/o ports. port 3 also serves the special features of the 80c51 family, as listed below. i/o rxd (p3.0): serial input port i/o txd (p3.1): serial output port
6 at8xc5111 4190a ? 8051 ? 11/02 i/o int0 (p3.2): external interrupt 0 i/o t0 (p3.3): timer 0 external input p4.0 - p4.7 i/o port 4 : port 4 is an 8-bit programmable i/o port with internal pull-ups. see section "ports", page 18 for a description of i/o ports. port 4 is also the input port of the analog-to-digital converter. i/o ain0 (p4.0): a/d converter input 0 i/o ain1 (p4.1): a/d converter input 1 t1: timer 1 external input i/o ain2 (p4.2): a/d converter input 2 ss : slave select input of the spi controllers i/o ain3 (p4.3): a/d converter input 3 int1 : external interrupt 1 i/o ain4 (p4.4): a/d converter input 4 miso: master in, slave out of the spi controllers i/o ain5 (p4.5): a/d converter input 5 mosi: master out, slave in of the spi controllers i/o ain6 (p4.6): a/d converter input 6 spsck: clock i/o of the spi controllers i/o ain7 (p4.7): a/d converter input 7 mnemonic type name and function
7 at8xc5111 4190a ? 8051 ? 11/02 clock system the at8xc5111 oscillator system provides a reliable clocking system with full mastering of speed versus cpu power trade off. several clock sources are possible: external clock input high-speed crystal or ceramic oscillator integrated high-speed rc oscillator the selected clock source can be divided by 2 - 512 before clocking the cpu and the peripherals. when x2 function is set, the cpu needs 6 clock periods per cycle. clocking is controlled by several sfr registers: oscon, ckcon0, ckcon1, ckrl. blocks description the at8xc5111 includes the following oscillators: crystal oscillator integrated high-speed rc oscillator, with typical frequency of 12 mhz crystal oscillator: osca the crystal oscillator uses two external pins, xtal1 for input and xtal2 for output. both crystal and ceramic resonators can be used. an oscillator source on xtal1 is mandatory to start the product. oscaen in osccon register is an enable signal for the crystal oscillator or the exter- nal oscillator input. integrated high-speed rc oscillator: oscb the high-speed rc oscillator typical frequency is 12 mhz. note that the on chip oscilla- tor has a 50% frequency tolerance and may not be suitable for use in some applications. oscben in osccon register is an enable signal for the high-speed rc oscillator. clock selector cks bit in cks register is used to select from crystal to rc oscillator. oscben bit in osccon register is used to enable the rc oscillator. oscaen bit in osccon register is used to enable the crystal oscillator or the external oscillator input. clock prescaler before supplying the cpu and the peripherals, the main clock is divided by a factor of 2 to 512, as defined by the ckrl register. the cpu needs from 12 to 256*12 clock peri- ods per instruction. this allows: to accept any cyclic ratio to be accepted on xtal1 input. to reduce the cpu power consumption. the x2 bit allows to bypass the clock prescaler; in this case, the cpu needs only 6 clock periods per machine cycle. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%.
8 at8xc5111 4190a ? 8051 ? 11/02 functional block diagram operating modes functional modes normal modes cpu and peripheral clocks depend on the software selection using ckcon0, ckcon1, cksel and ckrl registers. cks bit selects either xtal_osc or rc_osc. ckrl register determines the frequency of the selected clock, unless x2 bit is set. in this case the prescaler/divider is not used, so cpu core needs only 6 clock periods per machine cycle. according to the value of the peripheral x2 individual bit, each peripheral needs 6 or 12 clock periods per instruction. it is always possible to switch dynamically by software from xtal_osc to rc_osc, and vice versa by changing cks bit, a synchronization cell allowing to avoid any spike during transition. idle modes idle modes are achieved by using any instruction that writes into pcon.0 sfr idle modes a and b depend on previous software sequence, prior to writing into pcon.0 register: ? idle mode a: xtal_osc is running (oscaen = 1) and selected (cks = 1) ? idle mode b: rc_osc is running (oscben = 1) and selected (cks = 0) the unused oscillator xtal_osc or rc_osc can be stopped by software by clearing oscaen or oscben, respectively. exit from idle mode is achieved by reset, or by activation of an enabled interrupt. in both cases, pcon.0 is cleared by hardware. xtal2 xtal1 pwdrc wd clock pwdosc ckrl reload 8-bit prescaler-divider resetb 1 0 oscout xtal_osc rc_osc oscben oscaen cks x2 0 1 mux filter + osca oscb ckidle ck idle cpu clock peripherals clock pwd ckout ckadc quiet : 128 a/d clock sub clock timer 0 clock
9 at8xc5111 4190a ? 8051 ? 11/02 exit from idle modes will leave the oscillator control bits oscaen, oscben and cks unchanged. power-down modes power-down modes are achieved by using any instruction that writes into pcon.1 sfr exit from power-down mode is achieved either by a hardware reset, or by an external interruption. by rst signal: the cpu will restart on osca. by int0 or int1 interruptions, if enabled. the oscillators control bits oscaen, oscben and cks will not be changed, so the selected oscillator before entering into power-down will be activated. prescaler divider an hardware reset selects the prescaler divider: ? ckrl = ffh: internal clock = oscout/2 (standard c51 feature) ? x2 = 0, after reset, any value between ffh down to 00h can be written by software into ckrl sfr in order to divide frequency of the selected oscillator: ? ckrl = 00h: minimum frequency = oscout/512 ? ckrl = ffh: maximum frequency = oscout/2 the frequency of the cpu and peripherals clock ckout is related to the frequency of the main oscillator oscout by the following formula: f ckout = f oscout /(512 - 2*ckrl) some examples can be found in the table below: a software instruction which sets x2 bit de-activates the prescaler/divider, so the internal clock is either xtal_osc or rc_osc depending on sel_osc bit. table 1. power modes pd idle cks oscben oscaen selected mode comment 0 0 1 x 1 normal mode a osca: xtal clock x x 1 x 0 invalid no active clock 0 0 0 1 x normal mode b oscb: high-speed rc clock xx 0 0 xinvalid 0 1 1 x 1 idle mode a the cpu is off, osca supplies the peripherics 0 1 0 1 x idle mode b the cpu is off, oscb supplies the peripherics 1xx x x total power- down the cpu is off, osca and oscb are stopped f oscout mhz x2 ckrl f ckout (mhz) 12 0 ff 6 12 0 fe 3 12 1 x 12
10 at8xc5111 4190a ? 8051 ? 11/02 timer 0: clock inputs the sclkt0 bit in osccon register allows to select timer 0 subsidiary clock. this allows to perform a real-time clock function. sclkt0 = 0: timer 0 uses the standard t0 pin as clock input (standard mode). sclkt0 = 1: timer 0 uses the special sub clock as clock input. when the subclock input is selected for timer 0 and the crystal oscillator is selected for cpu and peripherals, the ckrl prescaler must be set to ff (division factor 2) in order to assure a proper count on timer 0. with an external a 32 khz oscillator, the timer interrupt can be set from 1/256 to 256 seconds to perform a real-time clock (rtc) function. the power consumption will be very low as the cpu is in idle mode at 32 khz most of the time. when more cpu power is needed, the internal rc oscillator is activated and used by the cpu and the others peripherals. registers clock control register the clock control register is used to define the clock system behavior. table 2. osccon - clock control register (8fh) sclkt0 1 0 ckidle : 6 t0 pin sub clock c/t 1 0 osccon tmod gate int0 tr0 timer 0 control 76543210 -----sclkt0oscbenoscaen bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit.
11 at8xc5111 4190a ? 8051 ? 11/02 reset value = 0xxx x001b not bit addressable clock selection register the clock selection register is used to define the clock system behavior table 3. cksel - clock selection register (85h) reset value = xxxx xxx 1 b not bit addressable 2sclkt0 sub clock timer0 cleared by software to select t0 pin set by software to select t0 sub clock 1oscben enable rc oscillator this bit is used to enable the high-speed rc oscillator 0: the oscillator is disabled 1: the oscillator is enabled. 0oscaen enable crystal oscillator this bit is used to enable the crystal oscillator 0: the oscillator is disabled 1: the oscillator is enabled. bit number bit mnemonic description 76543210 ------cks bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0cks active oscillator selection this bit is used to select the active oscillator. 1: the crystal oscillator is selected. 0: the high-speed rc oscillator is selected.
12 at8xc5111 4190a ? 8051 ? 11/02 clock prescaler register this register is used to reload the clock prescaler of the cpu and peripheral clock. table 4. ckrl - clock prescaler register (97h) reset value = 1111 1111b not bit addressable clock control register this register is used to control the x2 mode of the cpu and peripheral clock. table 5. ckcon0 register (8fh) 76543210 m bit number bit mnemonic description 7: 0 ckrl 0000 0000b: division factor equal 512 1111 1111b: division factor equal 2 m: division factor equal 2*(256-m) 76543210 - wdx2 pcax2 six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7- reserved 6wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5pcax2 programmable counter array clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4six2 enhanced uart clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3- reserved 2t1x2 timer 1 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 1t0x2 timer 0 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle.
13 at8xc5111 4190a ? 8051 ? 11/02 reset value = x000 0000b not bit addressable table 6. ckcon1 register (afh) reset value = xxxx xx00b not bit addressable 0x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2" bits. 7 6 5 43210 - - - ---brgx2spix2 bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4- reserved 3- reserved 2- reserved 1brgx2 brg clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0 spix2 spi clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. bit number bit mnemonic description
14 at8xc5111 4190a ? 8051 ? 11/02 reset and power management the power monitoring and management can be used to supervise the power supply (v dd ) and to start up properly when at8xc5111 is powered up. it consists of the features listed below and explained hereafter: power-off flag idle mode power-down mode reduced emi mode all these features are controlled by several registers, the power control register (pcon) and the auxiliary register (auxr) detailed at the end of this section. aux register not available on all versions. functional description figure 1 shows the block diagram of the possible sources of microcontroller reset. figure 1. reset sources notes: 1. rst pin available only on 48 and 52 pins versions. 2. rst pin available only on lpc versions. power-off flag when the power is turned off or fails, the data retention is not guaranteed. a power-off flag (pof, table 8 on page 15) allows to detect this condition. pof is set by hardware during a reset which follows a power-up or a power-fail. this is a cold reset. a warm reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and pof. to use pof, test and clear this bit just after reset. then it will be set only after a cold reset. reset rst pin (1) hardware wd pca wd rst pin (2)
15 at8xc5111 4190a ? 8051 ? 11/02 registers pcon: power configuration register table 1. pcon register (87h) reset value = 0000 0000b port pins the value of port pins in the different operating modes is shown on table 9. table 2. pin conditions in special operating modes 76543210 smod1 smod0 ? pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 double baud rate bit set to double the baud rate when timer 1 is used and mode 1, 2 or 3 is selected in scon register. 6smod0 scon select bit when cleared, read/write accesses to scon.7 are to sm0 bit and read/write accesses to scon.6 are to sm1 bit. when set, read/write accesses to scon.7 are to fe bit and read/write accesses to scon.6 are to ovr bit. scon is serial port control register. 5 ? reserved must be cleared. 4pof power-off flag set by hardware when v dd rises above v ret+ to indicate that the power supply has been set off. must be cleared by software. 3gf1 general purpose flag 1 one use is to indicate wether an interrupt occurred during normal operation or during idle mode. 2gf0 general purpose flag 0 one use is to indicate wether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence. mode program memory port 1 pins port 3 pins port 4 pins reset don ? t care weak high weak high weak high idle internal data data data power-down internal data data data
16 at8xc5111 4190a ? 8051 ? 11/02 hardware watchdog timer (wdt) the wdt is intended as a recovery method in situations where the cpu may be sub- jected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr loca- tion 0a6h. when wdt is enabled, it will increment every machine cycle (6 internal clock periods) and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). the t0 bit of the wdtprg register is used to select the overflow after 10 or 14 bits. when wdt overflows, it will generate an internal reset. it will also drive an output reset high pulse at the emulator rst-pin. the length of the reset pulse is 24 clock periods of the wd clock. using the wdt to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) or 1024 (1fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96 x t osc , where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16 ms to 2s at f osc = 12 mhz and t0 = 0. to manage this fea- ture, refer to wdtprg register description, table 11 (sfr0a7h). table 1. wdtrst register wdtrst address (0a6h) write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 765 4 3 2 1 reset value x x x x x x x
17 at8xc5111 4190a ? 8051 ? 11/02 table 2. wdtprg register wdtprg address (0a7h) reset value = xxx0 0000 write only register wdt during power-down and idle power-down in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode the user does not need to service the wdt. there are 2 methods of exiting power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as normal whenever the at8xc5111 is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of power-down, it is best to reset the wdt just before entering power-down. idle mode in idle mode, the oscillator continues to run. to prevent the wdt from resetting the at8xc5111 while in idle mode, the user should always set up a timer that will periodi- cally exit idle, service the wdt, and re-enter idle mode. 76543210 t4 t3 t2 t1 t0 s2 s1 s0 bit number bit mnemonic description 7t4 reserved do not try to set this bit. 6t3 5t2 4t1 3t0 wdt overflow select bit 0: overflow after 14 bits 1: overflow after 10 bits 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 s2 s1 s0 selected time-out with t0 = 0 000 (2 14 - 1) machine cycles, 16.3 ms at 12 mhz 001 (2 15 - 1) machine cycles, 32.7 ms at 12 mhz 010 (2 16 - 1) machine cycles, 65.5 ms at 12 mhz 011 (2 17 - 1) machine cycles, 131 ms at 12 mhz 100 (2 18 - 1) machine cycles, 262 ms at 12 mhz 101 (2 19 - 1) machine cycles, 542 ms at 12 mhz 110 (2 20 - 1) machine cycles, 1.05 s at 12 mhz 111 (2 21 - 1) machine cycles, 2.09 s at 12 mhz
18 at8xc5111 4190a ? 8051 ? 11/02 ports the low pin count versions of the at8xc5111 has 3 i/o ports, port 1, port 3, and port 4. all port1, port3 and port4 i/o port pins on the at8xc5111 may be software configured to one of four types on a bit-by-bit basis, as shown in table 13. these are: quasi bi-direc- tional (standard 80c51 port outputs), push-pull, open drain, and input only. two configuration registers for each port choose the output type for each port pin. table 1. port output configuration settings using pxm1 and pxm2 registers port types quasi bi-directional output configuration the default port output configuration for standard at8xc5111 i/o ports is the quasi bi- directional output that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. one of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. the very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. the third pull-up is referred to as the "strong" pull-up. this pull-up is used to speed up low-to-high transitions on a quasi bi-directional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brief time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi bi-directional port configuration is shown in figure 2. pxm1.y bit pxm2.y bit port output mode 0 0 quasi bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain
19 at8xc5111 4190a ? 8051 ? 11/02 figure 1. quasi bi-directional output open-drain output configuration the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port configured in this manner must have an external pull-up, typically a resis- tor tied to v dd . the pull-down for this mode is the same as for the quasi bi-directional mode. the open-drain port configuration is shown in figure 3. figure 2. open-drain output push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open drain and the quasi bi-directional output modes, but provides a continuous strong pull- up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 4. 2 cpu input pin strong very weak n p p weak p clock delay port latch data data input pin n port latch data data
20 at8xc5111 4190a ? 8051 ? 11/02 figure 3. push-pull output input only configuration the input only configuration is a pure input with neither pull-up nor pull-down. the input only configuration is shown in figure 5. figure 4. input only ports description ports p1, p3 and p4 every output on the at8xc5111 may potentially be used as a 20 ma sink led drive out- put. however, there is a maximum total output current for all ports which must not be exceeded. all port pins of the at8xc5111 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. the inputs of each i/o port of the at8xc5111 are ttl level schmitt triggers with hysteresis. ports p0 and p2 the high pin-count version of the at8xc5111 has standard address and data ports p0 and p2. these ports are standard c51 ports (quasi bi-directional i/o). the control lines are provided on the pins: ale, psen, ea , reset; rd and wr signals are on the bits p1.1 and p1.0 . input pin strong n p port latch data data input pin data
21 at8xc5111 4190a ? 8051 ? 11/02 registers table 2. p1m1 address (d4h) reset value = 0000 00xx table 3. p1m2 address (e2h) reset value = 0000 00xx table 4. p3m1 address (d5h) reset value = 0000 0000 table 5. p3m2 address (e4h) reset value = 0000 0000 76543210 p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 bit number bit mnemonic description 7:0 p1m1.x port output configuration bit see table 10. for configuration definition 76543210 p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 bit number bit mnemonic description 7:0 p1m2.x port output configuration bit see table 10. for configuration definition 76543210 p3m1.7 p3m1.6 p3m1.5 p3m1.4 p3m1.3 p3m1.2 p3m1.1 p3m1.0 bit number bit mnemonic description 7:0 p3m1.x port output configuration bit see table 10 for configuration definition 76543210 p3m2.7 p3m2.6 p3m2.5 p3m2.4 p3m2.3 p3m2.2 p3m2.1 p3m2.0 bit number bit mnemonic description 7:0 p3m2.x port output configuration bit see table 10 for configuration definition
22 at8xc5111 4190a ? 8051 ? 11/02 table 6. p4m1 address (d6h) reset value = 0000 0000 table 7. p4m2 address (e5h) reset value = 0000 0000 76543210 p4m1.7 p4m1.6 p4m1.5 p4m1.4 p4m1.3 p4m1.2 p4m1.1 p4m1.0 bit number bit mnemonic description 7:0 p4m1.x port output configuration bit see table 10. for configuration definition. 76543210 p4m2.7 p4m2.6 p4m2.5 p4m2.4 p4m2.3 p4m2.2 p4m2.1 p4m2.0 bit number bit mnemonic description 7:0 p4m2.x port output configuration bit see table 10. for configuration definition.
23 at8xc5111 4190a ? 8051 ? 11/02 dual data pointer register the additional data pointer can be used to speed up code execution and reduce code size in a number of ways. the dual dptr structure is a way by which the chip will specify the address of an exter- nal data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 19) that allows the pro- gram code to switch between them (see figure 6). figure 1. use of dual pointer table 1. auxr1: auxiliary register 1 note: user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 76543210 -------dps bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0dps data pointer selection clear to select dptr0. set to select dptr1.
24 at8xc5111 4190a ? 8051 ? 11/02 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using one data pointer as a ? source ? pointer and the other one as a "destina- tion" pointer. assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,atdptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx atdptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a par- ticular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state.
25 at8xc5111 4190a ? 8051 ? 11/02 serial i/o ports enhancements the serial i/o ports in the at8xc5111 are compatible with the serial i/o port in the 80c52. they provide both synchronous and asynchronous communication modes. they oper- ate as universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simul- taneously and at different baud rates. serial i/o ports include the following enhancements: framing error detection automatic address recognition framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon regis- ter (see figure 7). figure 1. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 25) bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 8 and figure 9). figure 2. uart timings in mode 1 sm0 to uart mode control (smod0 = 0 for uart) ri ti rb8 tb8 ren sm2 sm1 idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control set fe bit if stop bit is 0 (framing error) (smod0 = 1 for uart) scon for uart (98h) (scon_1 for uart_1 (c0h)) pcon for uart (87h) (smod bits for uart_1 are located in bdrcon_1) sm0/fe data byte ri smod0 = x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0 = 1
26 at8xc5111 4190a ? 8051 ? 11/02 figure 3. uart timings in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled for each uart when the multipro- cessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device ? s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e., setting sm2 bit in scon register in mode 0 has no effect). given address each uart has an individual address that is specified in saddr register; the saden register is a mask byte that contains don ? t care bits (defined by zeros) to form the device ? s given address. the don ? t care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0010b saden 1111 1101b given1111 00x1b ri smod0 = 0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0 = 1 fe smod0 = 1
27 at8xc5111 4190a ? 8051 ? 11/02 the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don ? t care bit; for slaves b and c, bit 0 is a 1. to commu- nicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don ? t care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don ? t care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast = saddr or saden1111 111xb the use of don ? t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast1111 1x11b, slave c:saddr = 1111 0010b saden 1111 1101b broadcast1111 1111b for slaves a and b, bit 2 is a don ? t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don ? t care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. baud rate selection for uart for modes 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon registers.
28 at8xc5111 4190a ? 8051 ? 11/02 figure 4. baud rate selection table 1. baud rate selection table for uart internal baud rate generator (brg) when the internal baud rate generator is used, the baud rates are determined by the brg overflow depending on the brl reload value, the x2 bit in ckon0 register, the value of spd bit (speed mode) in bdrcon register and the value of the smod1 bit in pcon register (for uart). figure 5. internal baud rate generator tbck rbck clock source for uart tx clock source uart rx 0 0 timer 1 timer 1 10 int_brg timer 1 0 1 timer 1 int_brg 1 1 int_brg int_brg / 16 rbck int_brg 0 1 tbck int_brg timer1_brg rx clock / 16 0 1 timer1_brg tx clock peripheral clock brg 0 1 /6 brl /2 0 1 int_brg spd brr smod1 auto reload counter overflow
29 at8xc5111 4190a ? 8051 ? 11/02 for uart: example of computed value when x2 = 1, smod1 = 1, spd = 1 example of computed value when x2 = 0, smod1 = 0, spd = 0 the baud rate generator can be used for mode 1 or 3 (see figure 10), but also for mode 0 for both uarts, thanks to the bit src located in bdrcon register (see table 27). baud rates f xtal = 16.384 mhz f xtal = 24 mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc = 16.384 mhz f osc = 24 mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 baud_rate = 2 smod1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x [256 - (brl)] (brl) = 256 - 2 smod1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x baud_rate
30 at8xc5111 4190a ? 8051 ? 11/02 uart registers table 2. saden - slave address mask register for uart (b9h) reset value = 0000 0000b table 3. saddr - slave address register for uart (a9h) reset value = 0000 0000b table 4. sbuf - serial buffer register for uart (99h) reset value = xxxx xxxxb table 5. brl - baud rate reload register for the internal baud rate generator, uart - uart(9ah) reset value = 0000 0000b 76543210 76543210 76543210 76543210
31 at8xc5111 4190a ? 8051 ? 11/02 table 6. scon register scon - serial control register for uart (98h) reset value = 0000 0000b bit addressable 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7fe framing error bit (smod0 = 1) for uart clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 (smod0 = 0) for uart refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6sm1 serial port mode bit 1 for uart sm0 sm1 mode description baud rate 0 0 0 shift register f xtal /12 (f xtal /6 x2 mode) 0 1 1 8-bit uart variable 10 2 9-bit uart f xtal /64 or f xtal /32 (f xtal /32 or f xtal /16 x2 mode) 1 1 3 9-bit uart variable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit for uart clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4ren reception enable bit for uart clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 for uart . clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 for uart cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1ti transmit interrupt flag for uart clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag for uart clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 8 and figure 9 in the other modes.
32 at8xc5111 4190a ? 8051 ? 11/02 table 7. pcon register pcon - power control register (87h) reset value = 0001 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesn ? t affect the value of this bit. 76543210 smod1 smod0 rstd pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 for uart clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5rstd reset detector disable bit clear to disable pfd. set to enable pfd. 4pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general-purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general-purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
33 at8xc5111 4190a ? 8051 ? 11/02 table 8. bdrcon register bdrcon - baud rate control register (9bh) reset value = xxx0 0000b 76543210 - - - brr tbck rbck spd src bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4brr baud rate run control bit clear to stop the internal baud rate generator. set to start the internal baud rate generator. 3tbck transmission baud rate generator selection bit for uart clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2rbck reception baud rate generator selection bit for uart clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1spd baud rate speed control bit for uart clear to select the slow baud rate generator. set to select the fast baud rate generator. 0src baud rate source select bit in mode 0 for uart clear to select f osc /12 as the baud rate generator (f osc /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
34 at8xc5111 4190a ? 8051 ? 11/02 serial port interface (spi) the serial peripheral interface (spi) module which allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: full-duplex, three-wire synchronous transfers master operation eight programmable master clock rates serial clock with programmable polarity and phase master mode fault error flag with mcu interrupt capability write collision flag protection signal description figure 12 shows a typical spi bus configuration using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices: figure 1. typical spi bus the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected between the master device and a slave device. the mosi line is used to transfer data in series from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in series from the slave to the master. therefore, it is an output signal from the slave, and an input signal to the master. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data movement both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. it is obvious that only one master (ss high level) can drive the network. the master may select each slave device by software through port slave 1 miso mosi sck ss miso mosi sck ss port 0 1 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss v dd master
35 at8xc5111 4190a ? 8051 ? 11/02 pins (see figure 12). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see error conditions). baud rate in master mode, the baud rate can be selected from a baud rate generator which is con- troled by three bits in the spcon register: spr2, spr1 and spr0. the master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock. table 28 gives the different clock rates selected by spr2:spr1:spr0. table 1. spi master baud rate selection spr2:spr1:spr0 clock rate baud rate divisor (bd) 000 f ckidle /2 2 001 f ckidle /4 4 010 f ckidle /8 8 011 f ckidle /16 16 100 f ckidle /32 32 101 f ckidleh /64 64 110 f ckidle /128 128 111 external clock output of brg
36 at8xc5111 4190a ? 8051 ? 11/02 functional description figure 13 shows a detailed structure of the spi module. figure 2. spi module block diagram operating modes the serial peripheral interface can be configured as master mode only. the configura- tion and initialization of the spi module is made through one register: the serial peripheral control register (spcon) once the spi is configured, the data exchange is made using: spcon the serial peripheral status register (spsta) the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sam- pling on the two serial data lines (mosi and miso). when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 14). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /2 /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss ckidle /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - ---- external clk
37 at8xc5111 4190a ? 8051 ? 11/02 figure 3. full-duplex master-slave interconnection master mode the spi operates in master mode. only one master spi device can initiate transmis- sions. software begins the transmission from a master spi module by writing to the serial peripheral data register (spdat). if the shift register is empty, the byte is imme- diately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master ? s miso pin. the transmission ends when the serial peripheral transfer data flag, spif, in spsta becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spsta) with the spif bit set, and then reading the spdat. when the pin ss is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the spdat is present. transmission formats software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (1) ) and the clock phase (cpha (1) ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 15 and figure 16). the clock phase and polarity should be identical for the master spi device and the com- municating slave device. figure 4. data transmission format (cpha = 0) 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 1. before writing to the cpol and cpha bits, the spi should be disabled (spen = ? 0 ? ). msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number
38 at8xc5111 4190a ? 8051 ? 11/02 figure 16 shows an spi transmission in which cpha is ? 1 ? . in this case, the master begins driving its mosi pin on the first sck edge. therefore the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmis- sions (figure 17). this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 5. data transmission format (cpha = 1) figure 15 shows the first sck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 17). figure 6. cpha/ss timing msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 2 45678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
39 at8xc5111 4190a ? 8051 ? 11/02 error conditions the following flags in the spsta signal spi error conditions: mode fault (modf) mode fault error in master mode spi indicates that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. modf is set to warn that there may be a multi-master conflict for system control. in this case, the spi system is affected in the following ways: an spi receiver/error cpu interrupt request is generated. the spen bit in spcon is cleared. this disables the spi. the mstr bit in spcon is cleared. the modf flag is set when the ss signal becomes ? 0 ? . however, as stated before, for a system with one master, if the ss pin of the master device is pulled low, there is no way that another master is attempting to drive the net- work. in this case, clearing the modf bit is accomplished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its original set state after the modf bit has been cleared. write collision (wcol) a write collision (wcol) flag in the spsta is set when a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transfer continues uninterrupted. clearing the wcol bit is done through a software sequence of an access to spsta and an access to spdat. overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave device has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read of the spdat returns this byte. all others bytes are lost. this condition is not detected by the spi peripheral. interrupts two spi status flags can generate a cpu interrupt request: table 2. spi interrupts serial peripheral data transfer flag, spif: this bit is set by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt requests. mode fault flag, modf: this bit becomes set to indicate that the level on the ss is inconsistent with the mode of the spi. modf generates receiver/error cpu interrupt requests. flag request spif (sp data transfer) spi transmitter interrupt request modf (mode fault) spi receiver/error interrupt request (if ssdis = ? 0 ? )
40 at8xc5111 4190a ? 8051 ? 11/02 figure 18 gives a logical view of the above statements. figure 7. spi interrupt requests generation ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif
41 at8xc5111 4190a ? 8051 ? 11/02 registers there are three registers in the module that provide control, status and data storage functions. these registers are described in the following paragraphs. serial peripheral control register (spcon) the serial peripheral control register does the following: selects one of the master clock rates selects serial clock polarity and phase enables the spi module table 30 describes this register and explains the use of each bit: table 3. serial peripheral control register reset value = 00010100b 76543210 spr2 spen ?? cpol cpha spr1 spr0 bit number bit mnemonic r/w mode description 7spr2rw serial peripheral rate 2 bit with spr1 and spr0 define the clock rate 6spenrw serial peripheral enable clear to disable the spi interface set to enable the spi interface 5-rw reserved leave this bit at 0. 4-rw reserved leave this bit at 1. 3cpolrw clock polarity clear to have the sck set to ? 0 ? in idle state set to have the sck set to ? 1 ? in idle low 2cpharw clock phase clear to have the data sampled when the spsck leaves the idle state (see cpol) set to have the data sampled when the spsck returns to idle state (see cpol) 1spr1rw serial peripheral rate (spr2:spr1:spr0) 000: f ckidle /2 001: f ckidle /4 010: f ckidle /8 011: f ckidle /16 0spr0rw 100: f ckidle /32 101: f ckidle /64 110: f ckidle /128 111: external clock, output of brg
42 at8xc5111 4190a ? 8051 ? 11/02 serial peripheral status register (spsta) the serial peripheral status register contains flags to signal the following conditions. data transfer complete write collision inconsistent logic level on ss pin (mode fault error) table 31 describes the spsta register and explains the use of every bit in the register: table 4. serial peripheral status and control register reset value = 00x0xxxxb 76543210 spifwcol-modf---- bit number bit mnemonic r/w mode description 7spifr serial peripheral data transfer flag cleared by hardware to indicate data that transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6wcolr write collision flag cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. set by hardware to indicate that a collision has been detected. 5-rw reserved the value read from this bit is indeterminate. do not set this bit 4modfr mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approved by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level 3-rw reserved the value read from this bit is indeterminate. do not set this bit 2-rw reserved the value read from this bit is indeterminate. do not set this bit 1-rw reserved the value read from this bit is indeterminate. do not set this bit 0-rw reserved the value read from this bit is indeterminate. do not set this bit
43 at8xc5111 4190a ? 8051 ? 11/02 serial peripheral data register (spdat) the serial peripheral data register (table 32) is a read/write buffer for the receive data register. a write to spdat places data directly into the shift register. no transmit buffer is available in this model. a read of the spdat returns the value located in the receive buffer and not the content of the shift register. table 5. serial peripheral data register reset value = xxxx xxxxb r7:r0: receive data bits spcon, spsta and spdat registers may be read and written at any time while there is no on-going exchange. however, special care should be taken when writing to them while a transmission is on-going: do not change spr2, spr1 and spr0 do not change cpha and cpol do not change mstr clearing spen would immediately disable the peripheral writing to the spdat will cause an overflow 76543210 r7 r6 r5 r4 r3 r2 r1 r0
44 at8xc5111 4190a ? 8051 ? 11/02 programmable counter array (pca) the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accu- racy. the pca consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. its clock input can be programmed to count any one of the following signals: oscillator frequency 12 ( 6 in x2 mode) oscillator frequency 4 ( 2 in x2 mode) timer 0 overflow external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture software timer high-speed output pulse width modulator module 4 can also be programmed as a watchdog timer (see section "pca pwm mode", page 53). when the compare/capture modules are programmed in the capture mode, software timer, or high-speed output mode, an interrupt can be generated when the module exe- cutes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. the pca timer is a common time base for all five modules (see figure 19). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 33) and can be programmed to run at: 1/12 the oscillator frequency. (or 1/6 in x2 mode). 1/4 the oscillator frequency. (or 1/2 in x2 mode). the timer 0 overflow. the input on the eci pin (p1.2). pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1 16-bit module 2 p1.5/cex2 16-bit module 3 p1.6/cex3 16-bit module 4 p1.7/cex4
45 at8xc5111 4190a ? 8051 ? 11/02 figure 1. pca timer/counter cidl cps1 cps0 ecf it ch cl 16-bit up/down counter to pca modules fosc /12 fosc/4 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow table 1. cmod: pca counter mode register - cmod address 0d9h 76543210 cidl wdte - - - cps1 cps0 ecf bit number bit mnemonic description 7cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. 6wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. 5 - not implemented, reserved for future use. (1) 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.the value read from a reserved bit is indeterminate. 4 - not implemented, reserved for future use. 3 - not implemented, reserved for future use. 2cps1 cps1 cps0 selected pca input (2) 0 0 internal clock f osc /12 ( or f osc /6 in x2 mode). 0 1 internal clock f osc /4 ( or f osc /2 in x2 mode). 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f osc / 8) 2. f osc = oscillator frequency 1 cps0 pca count pulse select bit 0. 0ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. reset value = 00xxx00
46 at8xc5111 4190a ? 8051 ? 11/02 the cmod sfr includes three additional bits associated with the pca (see figure 19 and table 33). the cidl bit which allows the pca to stop during idle mode. the wdte bit which enables or disables the watchdog function on module 4. the ecf bit which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (see table 34). bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. bit cf: the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the watchdog timer function is implemented in module 4 (see figure 22). table 2. ccon: pca counter control register ccon address od8h 76543210 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 bit number bit mnemonic description 7cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. 6cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. 5 - not implemented, reserved for future use (1) . 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. 4 ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 3 ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 2 ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 1 ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 0 ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software.
47 at8xc5111 4190a ? 8051 ? 11/02 the pca interrupt system is shown in figure 20 below. figure 2. pca interrupt system pca modules: each one of the five compare/capture modules has six possible func- tions. it can perform: 16-bit capture, positive-edge triggered 16-bit capture, negative-edge triggered 16-bit capture, both positive and negative-edge triggered 16-bit software timer 16-bit high-speed output 8-bit pulse width modulator in addition, module 4 can be used as a watchdog timer. each module in the pca has a special function register associated with it. these regis- ters are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 35). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
48 at8xc5111 4190a ? 8051 ? 11/02 the last bit in the register ecom (ccapmn.6) when set enables the comparator function. table 35 shows the ccapmn settings for the various pca functions. table 3. ccapmn: pca modules compare/capture control registers capmn address n = 0 - 4 76543210 - ecomn cappn capn matn togn pwmm eccfn bit number bit mnemonic description 7 - not implemented, reserved for future use. (1) 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. 6 ecomn enable comparator. ecomn = 1 enables the comparator function. 5 cappn capture positive, cappn = 1 enables positive edge capture. 4 capnn capture negative, capnn = 1 enables negative edge capture. 3matn match. when matn = 1, a match of the pca counter with this module ? s compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. 2togn toggle. when togn = 1, a match of the pca counter with this module ? s compare/capture register causes the cexn pin to toggle. 1pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. 0 eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. reset value = x000000 table 4. pca module modes (ccapmn registers) ecomn cappn capnn matn togn pwmm eccfn module function 0000000no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x11000x 16-bit capture by a transition on cexn 100100x 16-bit software timer/compare mode. 1 0 0 1 1 0 x 16-bit high-speed output 10000108-bit pwm 1 0 0 1 x 0 x watchdog timer (module 4 only)
49 at8xc5111 4190a ? 8051 ? 11/02 there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 37 & table 38) table 5. ccapnh: pca modules capture/compare registers high ccapnh address n = 0 - 4 ccap0h = 0fah ccap1h = 0fbh ccap2h = 0fch ccap3h = 0fdh ccap4h = 0feh 76543210 reset value 00000000 table 6. ccapnl: pca modules capture/compare registers low ccapnl address n = 0 - 4 ccap0l = 0eah ccap1l = 0ebh ccap2l = 0ech ccap3l = 0edh ccap4l = 0eeh 76543210 reset value 00000000 table 7. ch: pca counter high ch address 0f9h 76543210 reset value 00000000 table 8. cl: pca counter low cl address 0e9h 76543210 reset value 00000000
50 at8xc5111 4190a ? 8051 ? 11/02 pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the mod- ule (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module ? s capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (see figure 21). figure 3. pca capture mode cf cr ccon 0xd8 ch cl ccapnh ccapnl ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca counter/timer ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
51 at8xc5111 4190a ? 8051 ? 11/02 16-bit software timer/ compare mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module ? s capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 22). figure 4. pca compare mode and pca watchdog timer note: 1. only for module 4 before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could occur. writing to ccapnh will set the ecom bit. once ecom is set, writing ccapnl will clear ecom so that an unwanted match doesn ? t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match ccon 0xd8 pca it enable pca counter/timer reset (1) cidl cps1 cps0 ecf cmod 0xd9 wdte reset write to ccapnl write to ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 10
52 at8xc5111 4190a ? 8051 ? 11/02 high-speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module ? s capture registers. to activate this mode the tog, mat, and ecom bits in the module ? s ccapmn sfr must be set (see figure 23). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. figure 5. pca high-speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could happen. once ecom is set, writing ccapnl will clear ecom so that an unwanted match doesn ? t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 24 shows the pwm func- tion. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the mod- ule's ccapln sfr the output will be low, when it is equal to or greater than, the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0
53 at8xc5111 4190a ? 8051 ? 11/02 figure 6. pca pwm mode an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 22 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer 2. periodically change the pca timer value so it will never match the compare val- ues or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca mod- ules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most appli- cations the first solution is the best option. this watchdog timer won ? t generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8-bit comparator cexn ? 0 ? ? 1 ? enable pca counter/timer overflow < >
54 at8xc5111 4190a ? 8051 ? 11/02 analog-to-digital converter (adc) this section describes the on-chip 10-bit analog-to-digital converter of the t89c51rb2/rc2. eight adc channels are available for sampling of the external sources an0 to an7. an analog multiplexer allows the single adc to select one of the 8 adc channels as adc input voltage (adcin). adcin is converted by the 10 bit-cas- caded potentiometric adc. three kind of conversions are available: standard conversion (7-8 bits). precision conversion (8-9 bits). accurate conversion (10 bits). for the precision conversion, set bits psidle and adsst in adcon register to start the conversion. the chip is in a pseudo-idle mode, the cpu doesn ? t run but the periph- erals are always running. this mode allows digital noise to be lower, to ensure precise conversion. for the accurate conversion, set bits quietm and adsst in adcon register to start the conversion. the chip is in a quiet mode, the ad is the only peripheral running. this mode allows digital noise to be as low as possible, to ensure high precision conversion. for these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. if another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. features 8 channels with multiplexed inputs 10-bit cascaded potentiometric adc conversion time down to 10 micro-seconds zero error (offset) 2 lsb max external positive reference voltage range 2.4 to v cc adcin range 0 to v cc integral non-linearity typical 1 lsb, max. 2 lsb (with 0.9*v cc 55 at8xc5111 4190a ? 8051 ? 11/02 figure 1. adc description figure 26 shows the timing diagram of a complete conversion. for simplicity, the figure depicts the waveforms in idealized form and does not provide precise timing informa- tion. for adc characteristics and timing parameters refer to the section ? ac characteristics ? of the at8xc5111 datasheet. figure 2. timing diagram note: tsetup = 4 s ain0/p4.0 ain1/p4.1 ain2/p4.2 ain3/p4.3 ain4/p4.4 ain5/p4.5 ain6/p4.6 ain7/p4.7 000 001 010 011 100 101 110 111 sch2 adcon.2 sch0 adcon.0 sch1 adcon.1 conv_ck aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrupt request eadc ie1.1 control avss sample and hold addh vref r/2r dac 8 10 + - addl 2 sar adcin vagnd vadref aden adcon.5 aden adsst adeoc t setup t conv conv_ck
56 at8xc5111 4190a ? 8051 ? 11/02 adc operation before starting a conversion, the a/d converter must be enabled, by setting the aden bit, for at least t setup (four microseconds). a start of single a/d conversion is triggered by setting bit adsst (adcon.3). from the adsst set, the first full conv_ck period will be the sampling period for the adc; during this period, the switch is closed and the capacitor is being charged. at the end of the first period, the switch opens and the capacitor is no longer being charged. during the next 10 conv_ck periods, the sample and hold will be in hold mode during the conversion. the busy flag adsst(adcon.3) remains set as long as an a/d conver- sion is running. after completion of the a/d conversion, it is cleared by hardware. when a conversion is running, this flag can be read only, a write has no effect. the end-of-conversion flag adeoc (adcon.4) is set when the value of conversion is available in addh and addl, it is cleared by software. if the bit eadc (ie1.1) is set, an interrupt occur when flag adeoc is set (see figure 28). clear this flag for re-arming the interrupt. from this point, if you keep starting a new conversion by resetting adsst without changing aden, it is not necessary to wait t setup . the bits sch0 to sch2 in adcon register are used for the analog input channel selection. before starting normal power reduction modes the adc conversion has to be com- pleted. table 1. selected analog input voltage conversion when the adcin is equal to varef, the adc converts the signal to 3ffh (full scale). if the input voltage equals vagnd, the adc converts it to 000h. input voltage between varef and vagnd are a straight-line linear conversion. all other voltages will result in 3ffh if greater than varef and 000h if less than vagnd. note that adcin should not exceed varef absolute maximum range. sch2 sch1 sch0 selected analog input 000an0 001an1 010an2 011an3 100an4 101an5 110an6 111an7
57 at8xc5111 4190a ? 8051 ? 11/02 clock selection the maximum clock frequency for adc (conv_ck for conversion clock) is defined in the ac characteristics section. a prescaler is featured (adcclk) to generate the conv_ck clock from the oscillator frequency. figure 3. a/d converter clock the conversion frequency conv_ck is derived from the oscillator frequency with the following formulas: f ckadc = f oscout /(512 - 2*ckrl) , if x2 = 0 = f oscout , if x2 = 1 and f conv_ck = f ckadc /(2*prs), if prs > 0 f conv_ck = f ckadc /256, if prs = 0 some examples can be found in the table below: adc standby mode when the adc is not used, it is possible to set it in standby mode by clearing bit aden in adcon register. in this mode the power dissipation is about 1 w. voltage reference the vref pin is used to enter the voltage reference for the a/d conversion. best accuracy is obtained with 0.9 v cc < v ref < v cc . it adc management an interrupt end-of-conversion will occur when the bit adeoc is activated and the bit eadc is set. to re-arm the interrupt the bit adeoc must be cleared by software. figure 4. adc interrupt structure prescaler adclk a/d converter conv_ck ckadc /2 f oscout mhz x2 ckrl f ckadc mhz adclk f conv_ck khz conversion time s 16 0 ff 8 12 333 33 16 1 na 16 32 250 44 adeoc adcon.2 eadc ie1.1 adci
58 at8xc5111 4190a ? 8051 ? 11/02 registers table 2. adcon register adcon (s:f3h) adc control register reset value = x000 0000b table 3. adclk register adclk (s:f2h) adc clock prescaler reset value = 0000 0000b 76543210 quietm psidle aden adeoc adsst sch2 sch1 sch0 bit number bit mnemonic description 7quietm pseudo idle mode (best precision) set to put in quiet mode during conversion. cleared by hardware after completion of the conversion. 6psidle pseudo idle mode (good precision) set to put in idle mode during conversion. cleared by hardware after completion of the conversion. 5aden enable/standby mode set to enable adc. clear for standby mode (power dissipation 1 w). 4adeoc end of conversion set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3adsst start and status set to start an a/d conversion. cleared by hardware after completion of the conversion. 2 - 0 sch2:0 selection of channel to convert see table 41. 76543210 - prs 6 prs 5 prs 4 prs 3 prs 2 prs 1 prs 0 bit number bit mnemonic description 7 ? reserved leave this bit at 0. 6 - 0 prs6:0 clock prescaler f conv_ck = f ckadc /(2 * prs) if prs = 0, f conv_ck = f ckadc /256
59 at8xc5111 4190a ? 8051 ? 11/02 table 4. addh register addh (s:f5h read only) adc data high byte register read only register reset value = 00h table 5. addl register addl (s:f4h read only) adc data low byte register read only register reset value = xxxx xx00b table 6. adcf register adcf (s:f6h) adc input select register 76543210 adat 9 adat 8 adat 7 adat 6 adat 5 adat 4 adat 3 adat 2 bit number bit mnemonic description 7 - 0 adat9:2 adc result bits 9 - 2 76543210 - - - - - - adat 1 adat 0 bit number bit mnemonic description 7 - 6 - reserved the value read from these bits are indeterminate. do not set these bits. 1 - 0 adat1:0 adc result bits 1 - 0 76543210 sel7 sel6 sel5 sel4 sel3 sel2 sel1 sel0 bit number bit mnemonic description 7 - 0 sel7 - 0 select input 7 - 0 set to select bit 7 - 0 as possible input for a/d cleared to leave this bit free for other function
60 at8xc5111 4190a ? 8051 ? 11/02 interrupt system the at8xc5111 has a total of 8 interrupt vectors: two external interrupts (int0 and int1 ), two timer interrupts (timers 0, 1), serial port interrupt, pca, spi and a/d. these interrupts are shown in figure 29. figure 1. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register (see table 49). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt priority register (see table 51) and in the interrupt priority high register (see table 53). table 47 shows the bit values and priority levels associated with each combination. ie1 0 3 high priority interrupt interrupt polling sequence low priority interrupt global disable individual enable ti ri tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 nc spi 0 3 adc 0 3 0 3 cf ccfx pca
61 at8xc5111 4190a ? 8051 ? 11/02 table 1. priority bit level values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt can ? t be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 2. address vectors iph.x ip.x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest) interrupt name interrupt address vector priority number external interrupt (int0) 0003h 1 timer0 (tf0) 000bh 2 external interrupt (int1) 0013h 3 timer1 (tf1) 001bh 4 pca (cf or ccfn) 0033h 5 uart (ri or ti) 0023h 6 spi 004bh 8 adc 0043h 9
62 at8xc5111 4190a ? 8051 ? 11/02 table 3. ie0 register ie0 - interrupt enable register (a8h) reset value = 00x0 0000b bit addressable 76543210 ea ec - es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6ec pca interrupt enable clear to disable the the pca interrupt. set to enable the the pca interrupt. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
63 at8xc5111 4190a ? 8051 ? 11/02 table 4. ie1 register ie1 (s:b1h) - interrupt enable register reset value = xxxx x00xb no bit addressable 76543210 -----espieadc- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2 espi spi interrupt enable bit clear to disable the spi interrupt. set to enable the spi interrupt. 1eadc a/d interrupt enable bit clear to disable the adc interrupt. set to enable the adc interrupt. 0- reserved the value read from this bit is indeterminate. do not set this bit.
64 at8xc5111 4190a ? 8051 ? 11/02 table 5. ipl0 register ipl0 - interrupt priority register (b8h) reset value = x0x0 0000b bit addressable. 76543210 - ppc - ps pt1 px1 pt0 px0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ppc pca counter interrupt priority bit refer to ppch for priority level. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4ps serial port priority bit refer to psh for priority level. 3pt1 timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1 external interrupt 1 priority bit refer to px1h for priority level. 1pt0 timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0 external interrupt 0 priority bit refer to px0h for priority level.
65 at8xc5111 4190a ? 8051 ? 11/02 table 6. ipl1 register ipl1 - interrupt priority low register 1 (s:b2h) reset value = xxxx x00xb not bit addressable. 76543210 -----pspipadc- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2pspi spi interrupt priority level less significant bit. refer to pspih for priority level. 1padc adc interrupt priority level less significant bit. refer to padch for priority level. 0- reserved the value read from this bit is indeterminate. do not set this bit.
66 at8xc5111 4190a ? 8051 ? 11/02 table 7. iph0 register iph0 - interrrupt priority high register reset value = x0x0 0000b not bit addressable 76543210 - ppch - psh pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ppch pca counter interrupt priority level most significant bit ppch ppc priority level 0 0 lowest 01 10 1 1 highest 5- reserved the value read from this bit is indeterminate. do not set this bit. 4psh serial port priority high bit psh ps priority level 0 0 lowest 01 10 1 1 highest 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1 priority level 0 0 lowest 01 10 1 1 highest 2px1h external interrupt 1 priority high bit px1h px1 priority level 0 0 lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0 priority level 0 0 lowest 01 10 1 1 highest 0px0h external interrupt 0 priority high bit px0h pt0 priority level 0 0 lowest 01 10 1 1 highest
67 at8xc5111 4190a ? 8051 ? 11/02 table 8. iph1 register iph1 - interrupt high register 1 (b3h) reset value = xxxx x00xb not bit addressable 76543210 -----pspihpadch- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2 pspih spi interrupt priority level most significant bit psp1h psp1 priority level 0 0 lowest 01 10 1 1 highest 1 padch adc interrupt priority level most significant bit padch padc priority level 0 0 lowest 01 10 1 1 highest 0- reserved the value read from this bit is indeterminate. do not set this bit.
68 at8xc5111 4190a ? 8051 ? 11/02 rom rom s t ru c t ure t he a t 8 3 c51 1 r o m me m o r y is d i v i ded in th r ee d i ffe r e n t a r r a y s : the code array: ................................................................................4k bytes the encryption array: .......................................................................64 bytes the signature array:..........................................................................4 bytes rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. encryption array within the rom array there are 64 bytes of encryption array. every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nor ? ed (xnor) with the code byte, creat- ing an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be pro- grammed with random values. configuration byte the configuration byte is a special register. its content, described in paragraph section ? registers ? , page 10 is defined by the diffusion mask in the rom version or writ- ten by the otp programmer in the otp version. the lock bits when programmed according to table 55 will provide different levels of protection for the on-chip code and data. notes: 1. u: unprogrammed 2. p: programmed *warning: when security bit is set, rom contend cannot be verified. only the crc is verified. signature bytes the t80c5111 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section ? signature bytes content ? , page 69. verify algorithm refer to section ? verify algorithm ? , page 68. program code mapping as there is no external capability in lpc packages, the code size is limited to 4k bytes. any access above 4k will be mapped in the first 4k segment (0xxxh). table 1. program lock bits program lock bits protection description security level lb1 lb2 1uu no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction returns non encrypted data. 2 p u same as 1 3up same as 2, also verify is disabled. this security level is available because rom integrity will be verified thanks to another method*.
69 at8xc5111 4190a ? 8051 ? 11/02 eprom eprom programming specific algorithm is implemented, use qualified device programmers from third party vendors. eprom erasure (windowed packages only) erasing the eprom erases the code array, the encryption array and the lock bits return- ing the parts to full functionality. erasure leaves all the eprom cells in a 1 ? s state (ff). erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ? ) to an integrated dose at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. an exposure of 1 hour is recommended with most of standard erasers. erasure of the eprom begins to occur when the chip is exposed to light with wave- length shorter than approximately 4,000 ? . since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. signature bytes signature bytes content the at8xc5111 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom signature bytes reading. table 56. shows the content of the signature byte for the at8xc5111. table 1. signature bytes content location contents comment 30h 58h manufacturer code: atmel 31h 57h family code: c51 x2 60h 2eh product name: at8xc5111 4k rom version 60h aeh product name: at8xc5111 4k otp version 61h efh product revision number: at8xc5111 rev.0
70 at8xc5111 4190a ? 8051 ? 11/02 configuration byte the configuration byte is a special register. its content is defined by the diffusion mask in the rom version or is read or written by the otp programmer in the otp version. this register can also be accessed as a read only register. table 2. configuration byte - conf (efh) reset value = 1111 111x 765432 10 lb1 lb2 lb3 1 1 1 1 1 bit number bit mnemonic description 7:5 - program memory lock bits see previous chapter for the definition of these bits. 4 - reserved leave this bit at 1. 3 - reserved leave this bit at 1. 2 - reserved leave this bit at 1. 1 - reserved leave this bit at 1. 0 - reserved leave this bit at 1.
71 at8xc5111 4190a ? 8051 ? 11/02 electrical characteristics absolute maximum ratings (1) power consumption measurement since the introduction of the first c51 devices, every manufacturer made operat ing i cc measurements under reset, which made sense for the designs were the cpu was run- ning under reset. in our new devices, the cpu is no longer active during reset, so the power consumption is very low but is not really representat ive of what will happen in the customer system. that ? s why, while keeping measurements under reset, we present a new way to measure the operat ing i cc : using an internal test rom, the following code is executed: label: sjmp label (80 fe) ports 1, 3, 4 are disconnected, rst = v cc , xtal2 is not connected and xtal1 is driven by the clock. this is much more representat ive of the real operat ing i cc . c = commercial.................................................... 0 c to 70 c i = industrial ....................................................... -40 c to 85 c storage temperat ure .................................... -65 c to +150 c voltage on v cc to v ss ...........................................-0.5v to +7v voltage on v pp to v ss .........................................-0.5v to +13v voltage on any pin to v ss...................................... -0.5v to v cc +0.5v power dissipat ion .......................................................... 1 w (2) notes: 1. s tresses at or above those listed under ? absolute maximum rat ings ? may cause permanent dam- age to the device. this is a stress rat ing only and functional operat ion of the device at these or any other conditions above those indicat ed in the operat ional sections of this specificat ion is not implied. exposure to absolute maximum rat ing conditions may affect device reliability. 2. this value is based on the maximum allowable die temperat ure and the thermal resistance of the package.
72 at8xc5111 4190a ? 8051 ? 11/02 dc parameters for standard voltage table 1. dc parameters in standard voltage t a = -40 c to +85 c; v ss = 0 v; v cc = 5v 10% symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4. (6) 0.3 0.45 1.0 v v v i ol = 100 a i ol = 1.6 ma i ol = 3.5 ma v oh output high voltage, ports 1, 3, 4. (6) mode pseudo bidirectionnel v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 a i oh = -30 a i oh = -60 a v cc = 5v 10% v oh2 output high voltage, ports 1, 3, 4. (6) mode push pull v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -100 a i oh = -1.6 ma i oh = -3.2 ma v cc = 5v 10% off impedance, ports 1, 3, 4. 6m ? r rst rst pullup resistor 50 90 (5) 200 k ? i il logic 0 input current ports 1, 3 and 4 -50 tbd a v in = 0.45v, port 1 & 3 v in = 0.45v, port 4 i li input leakage current 10 a 0.45v < v in < v cc i tl logic 1 to 0 transition current, ports 1, 3, 4 -650 av in = 2.0 v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current to be confirmed 20 (5) 50 a2.0v < v cc < 5.5v (3) i cc under reset power supply current maximum values, x1 mode (7) to be confirmed 3+ 0.4 freq (mhz) 5.8 at 12 mhz 7.4 at 16 mhz ma vcc = 5.5v (1) i cc operat ing power supply current maximum values, x1 mode (7) to be confirmed 3 + 0.6 freq (mhz) 10.2 at 12 mhz 12.6 at 16 mhz ma v cc = 5.5v (8) i cc idle power supply current maximum values, x1 mode (7) to be confirmed 3 + 0.3 freq (mhz) 3.9 at 12 mhz 5.1 at 16 mhz ma v cc = 5.5v (2) i cc operat ing power supply current oscb to be confirmed 6 ma v cc = 5.5v (8), at 12 mhz v ret supply voltage during power-down mode 2 v
73 at8xc5111 4190a ? 8051 ? 11/02 dc parameters for low voltage notes: 1. i cc under reset is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 34.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; v pp = rst = v cc . i cc would be slightly higher if a crystal oscillat or used 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; v pp = rst = v ss (see figure 32.). 3. power-down i cc is measured with all output pins disconnected; v pp = v ss ; xtal2 nc.; rst = v ss (see figure 33.). 4. not applicable. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperat ure and 5v. table 2. dc parameters in standard voltage t a = -40 c to +85 c; v ss = 0 v; v cc = 2.7 to 5.5v symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4. (6) 0.3 0.45 1.0 v v v i ol = 100 a i ol = 0.8ma i ol = 1.6ma v oh output high voltage, ports 1, 3, 4. (6) mode pseudo bi-directionnal v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 a i oh = -30 a i oh = -60 a v oh2 output high voltage, ports 1, 3, 4. (6) mode push pull v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -100 a i oh = -0.8 ma i oh = -1.6 ma off impedance, ports 1, 3, 4. 6m ? r rst rst pullup resistor 50 90 (5) 200 k ? i il logic 0 input current ports 1, 3 and 4 -50 tbd a v in = 0.45v, port 1 & 3 v in = 0.45v, port 4 i li input leakage current 10 a 0.45v < v in < v cc i tl logic 1 to 0 transition current, ports 1, 3, 4 -650 a v in = 2.0v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current to be confirmed 20 (5) 50 a2.0v < v cc < 5.5v (3) i cc under reset power supply current maximum values, x1 mode (7) tbd 1.5+ 0.2 freq (mhz) 3.4 at 12 mhz 4.2 at 16 mhz ma vcc = 3.3v (1) i cc operat ing power supply current maximum values, x1 mode (7) tbd 1.5 + 0.3 freq (mhz) 5.1 at 12 mhz 6.3 at 16 mhz ma v cc = 3.3v (8) i cc idle power supply current maximum values, x1 mode (7) tbd 1.5 + 0.15 freq (mhz) 2 at 12 mhz 2.6 at 16 mhz ma v cc = 3.3v (2) i cc operat ing power supply current oscb tbd 3 ma v cc = 3.3v (8), at 12mhz v ret supply voltage during power-down mode 2 v
74 at8xc5111 4190a ? 8051 ? 11/02 6. if i ol exceeds the test condition, v ol may exceed the relat ed specificat ion. pins are not guaranteed to sink current great er than the listed test conditions. 7. for other values, please contact your sales office. 8. operat ing i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 34.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; rst /v pp = v cc ;. the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillat or is used. measurements are made with otp products when possible, which is the worst case. figure 1. i cc test condition, under reset figure 2. operat ing i cc test condition v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc reset = v ss after a high pulse during at least 24 clock cycles v cc
75 at8xc5111 4190a ? 8051 ? 11/02 figure 3. i cc test condition, idle mode figure 4. i cc test condition, power-down mode figure 5. clock signal waveform for i cc tests in active and idle modes rst xtal2 xtal1 v ss v cc i cc v cc reset = v ss after a high pulse during at least 24 clock cycles v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnected. clock signal reset = v ss after a high pulse during at least 24 clock cycles v cc v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns.
76 at8xc5111 4190a ? 8051 ? 11/02 dc parameters for a/d converter t a = 0 c to +70 c; v ss = 0v; v cc = 2.7v to 5.5v . t a = -40 c to +85 c; v ss = 0v; v cc = 2.7v to 5.5v . table 3. dc parameters symbol parameter min typ max unit test conditions resolution 10 bit av in analog input voltage vss - 0.2 vcc + 0.2 v r ref resistance between v ref and vss 13 18 24 k ? cai analog input capacitance 60 pf during sampling integral non-linearity 1 2 lsb 0.9 vcc< v ref < vcc differential non-linearity 0.5 1 lsb 0.9 vcc< v ref < vcc offset error -2 2 lsb 0.9 vcc< v ref < vcc input source impedance 1 k ? for 10-bit resolution at maximum speed
77 at8xc5111 4190a ? 8051 ? 11/02 ac parameters explanat ion of the ac symbols each timing symbol has 5 characters. the first character is always a ? t ? (that stands for time). the other characters, depending on their positions, stand for the name of a sig- nal or the logical stat us of that signal. the following is a list of all the characters and what they stand for. example:t xhdv = time from clock rising edge to input dat a valid. t a = -40 c to +85 c (industrial temperat ure range); v ss = 0v; 2.7v < v cc < 5.5v ; -l range. table 61. gives the maximum applicable load capacitance for port 1, 3 and 4. timings will be guaranteed if these capacitances are respected. higher capacitance values can be used, but timings will then be degraded. table 4. load capacitance versus speed range, in pf table 63 gives the description of each ac symbols. table 64. gives for each range the ac parameter. table 65. gives the frequency derat ing formula of the ac parameter. to calculat e each ac symbols, take the x value corresponding to the speed grade you need ( -l) and replace this value in the formula. values of the frequency must be limited to the corre- sponding speed grade: table 5. max frequency for derat ing formula regarding the speed grade example: t xhdv in x2 mode for a -l part at 20 mhz (t = 1/20 e6 = 50 ns): x = 133 (table 65) t = 50 ns t xhdv = 5t - x = 5 x 50 - 133 = 117 ns -l port 1, 3 & 4 80 -l x1 mode, v cc = 5v -l x2 mode, v cc = 5v -l x1 mode, v cc = 3v -l x2 mode, v cc = 3v freq (mhz) 40 33 40 20 t (ns) 25 30 25 50
78 at8xc5111 4190a ? 8051 ? 11/02 serial port timing - shift register mode table 6. symbol description table 7. ac parameters for a fix clock table 8. ac parameters for a variable clock: derat ing formula symbol parameter t xlxl serial port clock cycle time t qvhx output dat a set-up to clock rising edge t xhqx output dat a hold after clock rising edge t xhdx input dat a hold after clock rising edge t xhdv clock rising edge to input dat a valid speed -l (v cc = 5v) x2 mode 33 mhz 66 mhz equiv. -l (v cc = 5v) standard mode 40 mhz -l (v cc = 3v) x2 mode 33 mhz 66 mhz equiv. -l (v cc = 3v) standard mode 40 mhz units symbol min max min max min max min max t xlxl 180 300 300 300 ns t qvhx 100 200 200 200 ns t xhqx 10 30 30 30 ns t xhdx 0000ns t xhdv 17 117 17 117 ns symbol type standard clock x2 clock -l (vcc = 5v) -l (vcc = 3v) units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 ns t xhqx min 2 t - x t - x 20 20 ns t xhdx min x x 0 0 ns t xhdv max 10 t - x 5 t- x 133 133 ns
79 at8xc5111 4190a ? 8051 ? 11/02 shift register timing waveforms figure 6. shift register timing waveforms table 9. external clock drive characteristics (xtal1) external clock drive waveforms figure 7. external clock drive waveforms va lid valid input data valid valid 0123456 8 7 clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri 01234567 valid valid valid valid instruction symbol parameter min max units t clcl oscillat or period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0 .7v cc 0.2v cc -0.1 v t chcl t clcx t clcl t clch t chcx
80 at8xc5111 4190a ? 8051 ? 11/02 a/d converter notes: 1. for 10 bits resolution ac testing input/output waveforms figure 8. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ? 1 ? and 0.45v for a logic ? 0 ? . timing measurement are made at v ih min for a logic ? 1 ? and v il max for a logic ? 0 ? . figure 9. float waveforms for timing purposes as port pin is no longer float ing when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20ma. clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by two. symbol parameter min typ max units tconv conversion time 11 clock periods (1 for sampling, 10 for conversion) tsetup setup time 4 s fconv_ck clock conversion frequency 1100 (1) khz sampling frequency 10 100 khz 0.45v v cc -0.5v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1 v v oh -0.1 v float v load v load +0.1 v v load -0.1 v
81 at8xc5111 4190a ? 8051 ? 11/02 figure 10. clock waveforms figure 39 indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagat ion also varies from output to output and component. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximat ely 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. clock xtal2 internal state4 state5 state6 state1 state2 state3 state4 state5 serial port shift clock port operation txd (mode 0) rxd sampled rxd sampled p1, p3, p4 pins sampled p1, p3, p4 pins sampled mov dest port (p1, p3, p4) (includes int0, int1, to, t1) old data new data p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2
82 at8xc5111 4190a ? 8051 ? 11/02 ordering information table 1. maximum clock frequency code -l (vcc = 5v) -l (vcc = 3v) unit standard mode, oscillator frequency standard mode, internal frequency 40 40 40 40 mhz x2 mode, oscillator frequency x2 mode, internal equivalent frequency 33 66 20 40 mhz table 2. possible order entries part number memory size (bytes) supply voltage temperature range max frequency (mhz) package packing at87c5111-3zsil 4k bytes otp 2.7 - 5.5v industrial 66 dil24 stick at87c5111-tdsil 4k bytes otp 2.7 - 5.5v industrial 66 so24 stick at87c5111-tdril 4k bytes otp 2.7 - 5.5v industrial 66 so24 tape & reel at87c5111-icsil 4k bytes otp 2.7 - 5.5v industrial 66 ssop24 stick at87c5111-icril 4k bytes otp 2.7 - 5.5v industrial 66 ssop24 tape & reel AT83C5111-3ZSIL 4k bytes rom 2.7 - 5.5v industrial 66 dil24 stick at83c5111-tdsil 4k bytes rom 2.7 - 5.5v industrial 66 so24 stick at83c5111-tdril 4k bytes rom 2.7 - 5.5v industrial 66 so24 tape & reel at83c5111-icsil 4k bytes rom 2.7 - 5.5v industrial 66 ssop24 stick at83c5111-icril 4k bytes rom 2.7 - 5.5v industrial 66 ssop24 tape & reel
83 at8xc5111 4190a ? 8051 ? 11/02 package drawings dil24
84 at8xc5111 4190a ? 8051 ? 11/02 so24
85 at8xc5111 4190a ? 8051 ? 11/02 ssop24
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